Resume

James W. Collier

Embedded Firmware & Hardware Systems – USC ECE

jwcollie@usc.edu | (916) 634-9400 | Los Angeles, CA | www.jwcollier.dev

Backgrounds Online – Corporate Intern (Onsite/Remote)

July 2024 – Present

Improved platform security issues and data integrity by identifying workflow vulnerabilities and implementing validation processes that improved production system reliability.
Validated internal data workflows and executed QA test cases to maintain platform security.

Defined structured RBAC permission hierarchies in collaboration with the engineering team to improve access segmentation and reduce unauthorized privilege exposure.
Led QA validation of platform features and jurisdiction-specific service data to identify inconsistencies.
Executed large-scale data integrity audits on background screening pipelines, identifying anomaly patterns and enforcing corrective validation controls within production environments.

Custom PCB RF Communication Device for Real-Time Chess Play

Designed and built a custom PCB-based embedded system, integrating an ESP32 MCU, NRF24L01 transceiver, ILI9341 LCD, and custom input controls on constrained hardware into a 3D-printed case, enabling real-time RF chess gameplay.
Designed and stabilized a shared SPI bus across ESP32, LCD, and NRF24L01 modules by implementing manual chip-select arbitration and validating CPOL/CPHA timing, eliminating signal integrity and power-related communication faults.
Implemented low-level embedded firmware in C using ESP-IDF, configuring GPIO, SPI transactions, interrupts, and peripheral drivers via serial logs and hardware isolation tests.

DC-Link Capacitor Degradation Detection in SiC Inverters

Engineered a high-fidelity digital twin of an 800 V SiC traction inverter and PMSM system, modeling switching dynamics and DC-link ripple under load using Python, NumPy, and SciPy.
Implemented state-space motor modeling, SPWM switching logic, and field-oriented control (FOC) to simulate DC-link voltage ripple and harmonic behavior under dynamic loads.
Designed a spectral degradation detection pipeline using FFT/STFT, signal feature extraction, and PyTorch-based regression models to estimate DC-link capacitor ESR growth from ripple signatures.

Cross-Layer Signal Impairment & Adaptive Control Framework

Developed a cross-layer framework that modeled signal-induced link degradation (SNR, BER, FEC effects) and dynamically adapted routing and congestion control to maintain stability in distributed systems under impaired network conditions.

University of Southern California – Bachelor of Science, Electrical and Computer Engineering

Expected May 2028 · Los Angeles, CA

Emphasis: Signals, Systems, and Learning

Hardware: ARM Cortex-M, ESP32, FreeRTOS, Peripheral Interfaces (SPI, I2C, UART, CAN, USB), KiCad, LTspice

Software: C, C++, Python, MATLAB, PyTorch, NumPy, SciPy, Verilog, VHDL, LEAN, LaTeX

Interests: Philosophy, Mathematics, Chess, Cooking, Tennis, Muay Thai, Film Analysis